搜索资源列表
async_transmitter
- 用verilog实现rs232通信async_transmitter.v-with verilog achieve rs232 communications async_transmitter.v
async_receiver
- 用verilog实现rs232 receiveri -with verilog achieve rs232 receiveri
uart
- 用Verilog实现的串口异步通信，适用于RS232
UART
- 用FPGA实现了RS232异步串行通信，所用语言是VHDL，另外本人还有Verilog的欢迎交流学习，根据RS232 异步串行通信来的帧格式，在FPGA发送模块中采用的每一帧格式为：1位开始位+8位数据位+1位奇校验位+1位停止位，波特率为2400。由设置的波特率可以算出分频系数，具体算法为分频系数X=CLK/(BOUND*2)。
b13c_environment
- rs232控制器，实现rs232的环境设置，verilog编写，所有权归opencores
Some_design_of_interface(IIC_P
- 一些接口电路的Verilog设计，主要包括IIC、PS2、矩阵键盘、RS232、还有一些基础试验的源代码如：除法器、多路选择器、加法器、减法器、8位优先编码器等。,Some design of interface(IIC，PS2,RS232...)
uart_fpga4fun
- rs232通信代码，在自己的xilinx开发板上已验证通过-rs232 code with verilog has been verified
Verilog_PS2_RS232
- 实现PS/2接口与RS-232接口的数据传输， PS/2键盘上按下按键，可以通过RS-232自动传送到主机的串口调试终端上，并在数据接收区显示接收到的字符。 串口调试终端的设置：波特率115200，一个停止位，无校验位。 -The realization of PS/2 interface with RS-232 data interface, PS/2 keyboard to press the button, through RS-232 automatic transmissi
UART
- 内含有完整的UART代码，包括发送和接受，且有testbench，可以直接仿真调试-Contain complete UART code, including send and receive and there testbench, can directly Simulation debugging
series_port
- 用verilog语言编写的串口收发程序，可以进行429总线数据与rs232口的通信。-With verilog program written in serial transceivers, can be 429 bus data and rs232 mouth communication.
chuankoumokuai
- 用VERILOG实现的串口RS232自收发模块，以通过板级测试。-RS232 serial port with the VERILOG achieve self-transceiver module, through board-level test.
PS2UART_verilog
- 基于Verilog的PS/2键盘接口实现,接收PS/2键盘数据，并转换成ASCII码，通过RS232发送到PC显示。-Based on Verilog, PS/2 keyboard interface, the receiving PS/2 keyboard data and convert it into ASCII code sent to the PC through the RS232 display.
homework_final_ver1
- 用verilog写的PS2键盘通过RS232与PC机通信，并且通信内容通过VGA显示-PS2 keyboard with verilog to write computer communication via RS232 with the PC and the communication content through VGA display
RS232-IPcore
- RS232 by verilog,ALTERA 的工程，由几个文件组成，可以参考学习-RS232 by verilog
04_uart_test
- 串行通信程序，Verilog示例程序，通用RS232(Serial communication program)
UART-Altera
- 使用Atera FPGA CycloneII 实现串口通信，遵循RS232协议。FPGA上的模块实现了数据的接收，取补码和发送。(Achieve serial communication with FPGA, following the protocol of RS232.)
RS232_verilog1
- RS232通信协议verilog程序。经过调试可以使用(RS232 communication protocol Verilog program. After debugging can be used)
UART1
- 基于Verilog的串口RS232控制器(RS232 controller of serial port based on Verilog)
UART
- Verilog写的UART 协议。可用于FPGA RS232接口实现。(The UART protocol written by Verilog. It can be used for the implementation of the FPGA RS232 interface.)
uart_rx
- Verilog实现的RS232发送和接收程序，有完成的verilog代码，testbench等。(UART send and receive verilog code, including verilog source code, testbench etc.)